Data expansion apparatus

ABSTRACT

When a data stream includes long sections of data that are repeated periodically, storage space may be saved by not including full repetitions of such sections in the storage. However, when the data is to be read from storage for utilization, the omitted repetitious sections must be inserted. This is accomplished by providing hardware apparatus which recognizes a particular flag occurring in the stored data. After recognizing the flag, the expansion apparatus interprets the next piece of information in the data stream as being the storage address of the start of a section of data that is to be inserted into the data stream; the next piece of information is interpreted as being the length of the section of data to be inserted; and the next following piece of information is the number of times that the section of data is to be inserted. The apparatus will respond to the flag and its associated indicators by inserting the appropriate data section the indicated number of times.

DETAILED DESCRIPTION BACKGROUND OF THE INVENTION

This invention relates to apparatus for expanding data that has geencompacted. More particularly, the invention relates to apparatus fordata expansion which is particularly useful in systems wherein long datasections of varying lengths are repetitively used varying numbers oftimes.

In systems such as the one described in U.S. Pat. No. 3,644,700 for"Method And Apparatus For Controlling An Electron Beam" by R. V. Kruppa,long sections of the same data are repetitively used over and overagain. The data used to control an electron beam are typically storedinitially on a magnetic disk, from which they are read into in a memorybuffer. From the buffer they are again read out and used for control ofthe beam. In a typical prior art system such as the one shown in thepatent, beam control data are read from a disk into the buffer, thesedata are used for beam control, and then the next block of beam controldata is read from the disk into the buffer. The amount of time that istaken for reading data from the disk into the buffer is a significantthroughout limiting factor. Also, a significant amount of space on thedisks can be required to hold all of the pattern data.

BRIEF DESCRIPTION OF THE INVENTION

This invention provides apparatus for expanding compacted data. Inaccordance with one aspect of the invention, while reading from thebuffer, the apparatus responds to a particular configuration within thedata stream, which configuration has replaced one or more repetitivedata sections. The configuration includes: a flag which uniquelyidentifies it to the apparatus; an address representing the location instorage of the repetitive data section; the length of the data section;and the number of times it is to be repeated. The expansion apparatusresponds to the above data format by inserting in place thereof theappropriate beam control data.

The primary advantage of this invention is that, by permitting thebuffer (and other intermediate storage devices) to store compresseddata, it enables the buffer to store a larger amount of beam controldata.

This leads to the further advantage that the buffer will need to berefilled from a disk less often than would otherwise be necessary. Sincethe disk-to-buffer operation is somewhat time consuming, use of thisinvention will increase throughput in the type of system mentionedabove.

It should also be noted that, with this invention, the compacted dataneed not contain any particular coded indications of the beginning orend of sections of data. All of the information necessary to locate thebeginning and end of a data section is contained in the informationwhich immediately follows the identifying flag. This leads to theadditional advantage that the repetitive data sections need not bear anyparticular relation to each other: that is, any two particular datasections could be completely separated from one another in storage, orthey could partially overlap one another, or one could be completelyincluded within the other.

The foregoing and other features and advantages of the invention will beapparent from the following more particular description of preferredembodiments of the invention as illustrated in the accompanying drawing.

In the drawings:

FIG. 1 is a schematic block diagram of a portion of a control systemwhich embodies this invention.

FIG. 2 shows an example of mechanism which could be used for keepingtrack of the length of a data section and of the number of times it hasbeen inserted in the data stream.

FIG. 3 shows the format of the flag which is inserted into the datastream for compaction.

FIG. 4 is a flow diagram showing the sequence of operations performed bya system embodying the invention.

FIG. 5 shows examples of compacted data.

DETAILED DESCRIPTION

FIG. 1 shows various aspects of a system embodying this invention. Astorage unit 2 is presumed to contain compacted data which may have beenloaded into it from a disk or other bulk storage medium (not shown).Associated with the storage unit 2 is a storage data register SDR 4through which data moves out of the storage unit. The storage unit isaddressed by a storage address register SAR 6. Data read from thestorage unit 2 will be gated through gate 8 to some apparatus 10 whichwill use the data. This apparatus could, for example, be the patterninput buffer of an electron beam control system, the central processingunit of a computer, etc. As data goes out of storage, it is examined bya decoder 12 which continually checks for the particular pattern orpatterns of bits that identify a situation where the data needs to beexpanded. This pattern is referred to as a "flag."

When the decoder 12 detects an expansion flag, it will produce a signalon line 14 to inhibit gate 8 from permitting passage of data from thestorage 2 to the using apparatus 10. The same signal that was used toinhibit gate 8 will, via line 16, enable another gate 18 to cause datato be passed from storage to a subroutine register 20. As will bedescribed in more detail below, the data in subroutine register 20 willcontrol insertion of repetitious data sections into the data stream.

In response to the flag, decoder 12 also causes the contents of SAR 6 tobe saved in an "old address register" OAR 22. This will subsequentlyenable normal transmission to resune at the proper address. Addressinformation contained in subroutine register 20 may be passed through anadder 24, where it may be combined with additional address informationcontained in a base address register BAR 26, and into the SAR 6. Thedecode mechanism 12 will then, via line 28, generate a storage readsignal. After subroutine register 20 has been loaded, decoder 12 willgenerate signals on lines 14 and 16 to enable gate 8 (to pass data fromstorage 2 to the using apparatus 10) and disable gate 18. Reading ofdata from storage 2 to the using apparatus 10 will then commence. Datawill be read from the storage unit commencing at the address supplied tothe SAR 6. Information concerning the length of the data section to beread, and the number of times that it is to be read, will be suppliedfrom the subroutine register 20 to a subroutine control mechanism 30.

After the appropriate data section has been inserted into the datastream from storage 2 to using apparatus 10 an appropriate number oftimes, the subroutine control 30 will cause the contents of OAR 22 to betransferred into the SAR 6 and normal processing will again continue.

Referring now to FIG. 3, the format of an "instruction" which causesdata expansion is shown. (The word "instruction" is used in its verygeneric sense to refer to a pattern of bits that initiates a particularaction in the hardware apparatus). The instruction comprises four fieldsutilizing a total of 48 bits. The first 8 bits are the flag which isdetected by the decoder 12 to cause initiation of data expansion. Thenext 24 bits represent the starting address in storage of the datasection that is to be inserted in the data stream. The next 12 bits arethe length of the data section, and the last 4 bits represent the numberof times that the data section is to be repeated. Using theconfiguration shown in FIG. 3, data sections containing up to 4095 unitsof information may be inserted as many as 15 times in response to one ofthese instructions. The precise meaning of a "unit of information" willdepend upon the system in which this invention is implemented,particularly upon the storage 2 and the manner in which it is addressed.For example, the unit of information could be a bit, a byte, a word,etc. The 40 bits comprising the address, length and count fields shownin FIG. 3 are the bits that are transmitted to the subroutine register20 shown in FIG. 1.

Referring now to FIG. 2, there is shown one embodiment of a mechanismthat could be used to implement the subroutine control 30. The lengthdata held in subroutine register 20 will be transferred to a lengthregister 32 and the count informtion held in subroutine register 20 willbe transferred to a count register 34. During this transfer, both thelength and count fields will be checked by zero detect circuits 36 and38, respectively, to determine whether either or both of these fieldscontains a zero. In the preferred embodiment of this invention, zeros inboth the length and count fields will be used to signify anunconditional change in the contents of SAR 6 with subsequentcontinuation of processing. This is similar to a programmedunconditional branch instruction. Zeros in both of these fields will bedetected by AND circuit 40 which will produce the branch signal at itsoutput. If one, but not both, of the length and count fields contains azero, an error condition will be signalled by the output of Exclusive-Orcircuit 42.

If neither of the length and count fields is zero, reading will commencefrom storage 2 at the address specified in SAR 6. With each storagereference, a signal on line 44 will cause the contents of lengthregister 32 to be decremented by one. The decrement signal appearing online 44 is preferably derived through a delay 46 from the storagereference signal which causes a readout from storage 2. Thus, thecontents of length register 32 will be decremented to "one" a very shorttime after the last data unit in the sqeuence has been read fromstorage. At this time, if count register 34 does not contain a one, asignal from one-detector 48 will: pass through gate 50 to again set SAR6 from the adder output latches AOL of adder 24; pass through gate 52 todecrement the count register 34; and present a signal on line 54 tocause the contents of length counter 32 to be set again from thesubroutine register 20. This sequence will continue until count register34 is finally decremented to one.

When count register 34 is decremented to one, one-detector 56 willproduce a signal which inhibits gate 50 (preventing a further attempt toset SAR 6 from the adder output latches) and inhibits gate 52(preventing further decrementation of count register 34). In order toprevent the possibility of a "race condition" caused by prematureoccurrence of an output from one-detector 56, it will be desirable toinclude a delay 58 in the path of the signal which decrements countregister 34.

After count register 34 has been decremented to one, subsequentdecrementation to one of length register 32 will produce a concurrenceof outputs from detectors 48 and 56, both of which feed the inputs ofAND 60. This concurrence will result in a signal from AND 60 which willbe utilized to transfer the contents of OAR 22 into SAR 6 so that thesystem can proceed with normal transmission of data from storage 2 tothe using apparatus 10. (Those skilled in the art will recognize that,depending upon the particular environment in which this invention isimplemented, the contents of OAR 22 will not necessarily be exactly theaddress that needs to be transferred in SAR 6 in order for normalprocessing to continue. However, in a typical system, any necessaryalteration of the OAR 22 contents prior to transfer to the SAR 6 willsimply be a matter of incrementing the contents of OAR 22 by a knownfixed amount. One manner of achieving this incrementation would be toinsert an adder 62 in the path between SAR 6 and OAR 22 as shown in FIG.1 so that the address going into OAR 22 is the address that willactually be needed to subsequently return the system to its normalprocessing mode.)

All of the elements shown in FIG. 2 are items that are well known in theart and need not be described in detail herein. For example, detectors36, 38, 48 and 56 could simply be implemented as comparators, each ofwhich receives a first input from an element as shown in FIG. 2. Thesecond input of each of the detectors 36 and 38 would be a fixed zero;the second input of each of detectors 48 and 56 would be a fixed one.

Referring now to FIG. 4, the sequence of operations of this invention isshown. As information is read from storage (block 100) it is checked(block 102) to see whether or not it contains a flag indicating thatdata expansion is required. When a flag is detected, the output of thestorage data register will be inhibited from being transmitted to theusing apparatus (block 104). The contents of the storage addressregister will be transferred into the old address register (block 106),with appropriate incrementing if necessary. Approximately in parallelwith the latter operation, address, length and count information will betransferred to the subroutine register (block 108). The addressinformation in the subroutine register will then, with any necessaryincrementation, be transferred to the storage address register (block110). The length and count information will be checked to see if eitheror both is equal to zero (blocks 112, 114 and 116). If both are equal tozero, the sequence will return to block 100 for continuation of normaldata transmission with a new address in the storage address register. Ifonly one of the length or count is equal to zero, an error signal willbe generated. If neither the count nor the length is equal to zero, aunit of data will be read from storage (block 118). After reading a unitof data, if the length register does not contain one (block 120), itwill be decremented (block 122) and another unit of data will be read(block 118). When the length register does contain a one (block 120),but the count register does not yet contain a one (block 124); the countregister will be decremented (block 126), the length register will beset again from the subroutine register (block 128), and the storageaddress register will be set (block 130) from the adder output latches(or directly from the subroutine register if incrementation capabilityis not included in the implementation) and the first unit of data in thedata sequence will again be read from storage (block 118). When thecontents of the length register has been decremented to one (block 120)after the contents of the count register also has been decremented toone (block 124) the data expansion will have been completed. Then, thecontents of the old address register will be transferred to the storageaddress register (block 132) and normal transmission of data fromstorage will continue (block 100).

Referring now to FIG. 5, manners are shown in which data could have beencompacted for use with this invention. The first line of FIG. 5 shows adata sequence ABCDCBACBABBDCD, wherein each of the letters A, B, C and Drepresents a different data sequence. Each of the four data sequencesrepresented in FIG. 5 may be of a different length, and each ispreferably somewhat longer than 48 bits (the length of the "instruction"which signals the apparatus to expand data). As an example, we shallassume that data sequence A is twice as long as an expand instruction;that B is four times as long; that C is three times as long; and that Dis five times as long. Also as an example, and for ease in description,we will regard the length of an expand instruction as being equal to one"unit". Thus, the sequence shown in the first line of FIG. 5 (comprisingthree A's, five B's, four C's and three D's) will occupy 53 units ofstorage if it is stored in uncompacted form.

The second line of FIG. 5 shows one manner in which this data could havebeen compacted for use in a system embodying this invention. The 15 datasequences have been compacted into four complete data sequences and nineexpand instructions, comprising a total of 23 units of storage -- almosta 57 percent saving. As shown in the second line of FIG. 5, each of thesequences A, B, C and D was included in its uncompacted form the firsttime that it was encountered. After that, each time that one of thesequences was encountered, it was replaced by a single expandinstruction. In FIG. 5, each of the expand instructions is representedby four lines indicating the four fields of the instruction. The firstline represents the flag which signals the apparatus that expansion isneeded. The second line is the address of the beginning of the datawhich is to be inserted in place of the instruction. For purposes ofthis example it has been assumed that the data shown is located incontiguous storage locations beginning at location zero. Thus, if thedata were to have been compacted as shown in the second line of FIG. 5,data segment A would begin at location zero, data segment B would beginat location two, data segment C would begin at location six and datasegment D would begin at location nine. In the representations ofinstructions, the third line is the length of the string of data that isto replace the instruction. For data segements A, B, C and D the lengthsare 2, 4, 3 and 5, respectively. Note that the last expand instruction,which has replaced the compound data segment CD, shows a length ofeight, the sum of the lengths of C and D. The fourth line in therepresentations of the expand instruction shows the number of times thatthe data segment is to be inserted. For the instructions shown all ofthe counts equal one except for the count in the instruction whichreplaces the compound data segment BB, for which the count equals two.

The third line of FIG. 5 shows another manner in which the data couldhave been compacted prior to being utilized in a system embodying thisinvention. Instead of utilizing an uncompacted data sequence the firsttime that the sequence is encountered, each of the sequences A, B and Cis not shown in expanded form until its second occurrence; the firstoccurrence of each of A, B and C is replaced by an expand instruction.In this example, the address of the beginning of each of the sequencesA, B, C and D (assuming that the first expand instruction is at locationzero) are locations 15, 11, 8 and 3, respectively. This alternative formof compaction enables the data sequence CBA to be replaced by a singleexpand instruction instead of the three instructions that were needed inthe previous example. This latter example of compaction utilizestwenty-one units of storage: a saving of over sixty percent over theuncompacted data; and a saving of almost nine percent as compared to thefirst example.

Although the point is not illustrated in either of the above examples,those skilled in the art will recognize that savings in storage spacecan often be realized by including some repetitious data segments morethan once. For example, if one had a situation where each of thecompound data segments AB, AC and AD were repeated several times, itcould be advantageous to include each of the three compound segments inits uncompacted form even though this would include three uncompacted Asegments. Then, each of the three compound data segments could bereplaced by a single expand instruction, resulting in a net saving ofstorage space.

As was mentioned above in the description of FIG. 1, an address which istransmitted from subroutine register 20 to SAR 6 may be incremented inan adder 24 by the contents of a base address register BAR 126. Thisincrementation will be particularly desirable in situations where, whenthe data are originally compacted, the address of the block of storagein which the data will ultimately reside is not precisely known. Inthese situations, the address information that will be put in the expandinstructions will comprise, for each data segment, the displacement ofthat segment from the beginning of a larger block of data. When theblock of data is loaded into storage 2, the storage address at which itbegins will be loaded into BAR 26 via initial load line 64 so that, whenexpansion is needed, appropriate addresses may be provided through adder24. By permitting blocks of data to be loaded into different portions ofstorage at different times, this enhances the flexibility of the system.An additional enhancement to system flexibility may be provided byincluding an option as to whether or not addresses contained insubroutine register 20 will be incremented by the contents of BAR 26.This can be accomplished by utilizing two different variations of theflag which identify the expand instruction. One flag will be used whenthe address contained in the expand instruction needs to be incrementedby a base address and, in this case, the apparatus will function as hasbeen described above. Another flag configuration can be used to indicatethat the address contained in the expand instruction is an absoluteaddress that requires no incrementation. In response to this latterflag, the decoder 12 can generate a signal which is fed via an inhibitline 66 to a gate 68 to prevent the contents of BAR 26 from being gatedto the adder 24. Of course, other addressing schemes (for example, avirtual addressing system) could be used if desired.

Those skilled in the art will recognize that, in the embodimentdescribed in detail herein, data that are referred to by an expandinstruction should not contain another expand instruction. Theadvantages potentially available with this invention could be increasedby providing the ability to have expand instructions within data thatis, itself, referred to by an expand instruction. This could readily beaccomplished by adding additional subroutine registers 20 in series withthe one shown, and adding additional old address registers 22 in serieswith the one shown. If this were to be done, it would also be desirableto add some checking circuitry to insure tha the retention capability ofthe OAR and subroutine register stacks is not exceeded by successiveexpansion-within-expansion references. Such checking circuitry is notutilized in the embodiment described herein. One manner in whichchecking could be inserted would utilize a mode latch. When a flag isdetected, the latch would be set to indicate expand mode. Afterexpansion is completed, the latch would be reset. An error would besignalled if another flag was detected while the mode latch was set.

There are a large number of arrangements that could be used forcompacting the data, all of which can be used as inputs to a systemembodying this invention. For example, in some applications it might bepractical to maintain in storage at all times a fixed set of datapatterns (which could, but need not, comprise all of the data patternsrequired for the application). This would eliminate the need torepetitively reload such patterns into storage as the data in storageare exhausted and new data are requested.

Any suitable methodology may be used for compacting the data that areused as inputs to a system embodying this invention. In a system such asthe one described in the Kruppa patent referred to above, the repetitivenature of certain data segments will be readily observed when the inputdata are created and can easily be compacted at that time.

Thos skilled in the art will also recognize that the "data" which areused as inputs to this system could be of various types such as, forexample, numeric information or computer programs. If the usingapparatus were to be the execution unit of a digital computer, forexample, this invention could be utilized to cause the computer toexecute a particular subroutine that is outside the sequential stream ofinstructions and to then automatically return to the sequentialinstruction stream.

Although the preferred embodiments of this invention recognize the endof a data expansion when both the length and count have been decrementedto "one", those skilled in the art will recognize that other techniques,for example, decrementation to "zero" could also have been used.Furthermore, although this embodiment shows the use of a length register(32 in FIG. 2) which is decremented to determine when the end of anexpansion data segment has been reached, the precise implementation ofthis portion of the invention will be determined to a large extent bythe environment in which the invention is implemented. Again, details ofsuch implementation are well known to those skilled in the art and neednot be expanded upon herein.

In the above embodiment, length was decremented when storage wasreferenced. In a system wherein more than one unit of data is set intothe SDR, decrementation of length would occur with each unit of dataread from the SDR.

Although it will generally be desirable to have the capability ofincrementing addresses contained in the subroutine register by thecontents of a base address register, in a relatively simple systemwherein the absolute address of each data segment is known beforehand,the inclusion of a base address register and an adder (26 and 24,respectively, in FIG. 1) might not be necessary.

Various requisites of any implementation of this invention, such as, forexample, timing and gating signals, delays (to avoid "race conditions"),etc, will be dependent upon the details of the environment in which theinvention is implemented. The size of the various fields in the expandinstruction will depend upon details (such as op code structure, memorysize, etc.) of the environmental system. Of course, the sequence ofthese fields could be charged if desired. Also, in many implementations,various aspects of the invention that are shown, most particularly, inFIGS. 1 and 2 will be somewhat distributed throughout the environmentalsystem. For example, the decoder 12 (FIG. 1) would, in many cases,actually be integrated within the control store of a host system. Theforegoing description of a preferred embodiment of the inventioncontains sufficient information so that one skilled in the art would beable to readily implement this invention in any given environment.

If this invention were implemented in a system wherein memory readoperations are terminated by a readout from a memory location specifiedin a termination register, there would be no need for a length register(32 in FIG. 2) in the subroutine control. The end of the data sectioncould be determined by adding the length held in the subroutine registerto the starting address also contained therein. Alternatively, in such asystem, the expand instruction could contain the ending address insteadof the length. However the number of bits in a typical address is largeenough (compared to the number of bits in a typical length field) sothat compaction efficiency would be adversely affected if two completeaddresses were used. Of course, the ending address (or, indeed, even theaddress used in the embodiment described in detail above) could be apartial address, but we prefer to avoid the slight additionalcomplexities that would be added if partial addresses were to be used.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that the above and other changes in form anddetails may be made therein without departing from the spirit and scopeof the invention.

What is claimed is:
 1. Data expansion apparatus for processing data tobe transmitted to a using device, comprising:storage means having anoutput and containing addressable storage locations storing a mixture ofdata and compact representations of data; said compact representationsof data each including a coded flag signifiying that it is a compactrepresentation;an address field identifying the initial location addressin said stoarge means of a predetermined data sequence; a length fieldindicating the length of said sequence; and a count field indicating apredetermined number of repetitions of said sequence to be sequentiallytransmitted to said using device; gating means connecting the output ofsaid storage means to said using device for transmission of data fromsaid storage means to said using device; deconding means connected tothe output of said storage means; said decoding means being responsiveto the occurrence of a flag at the output of said storage means toinhibit said gating means, thereby interrupting transmission of datafrom said storage means to said using device, said flag having been readfrom a storage location having an address n; first register means; meansresponsive to the occurrence at the output of said storage means fo saidaddress field, said length field and said count field to cause saidfirst register means to store indications of the initial location, thelength and the number of repetitions, respectively, of said sequence;means to cause transmission of said sequence from said storage means tosaid using device; and control means responsive to the completion oftransmission of said sequence the number of repetitions indicated insaid first register means to cause recommencement of storage access fromthe storage location which has and address of n + i, where i equals thelength of a compact representation of data.
 2. The data expansionapparatus of claim 1 wherein said control means includes:a lengthregister; means connecting said first register means to said lengthregister to cause said length register to store said indication of thelength of said sequence; first decrementing means responsive totransmissions of data from said storage means to said using device tocause decrementation of said length register; first detecting meansconnected to said length register for generating a first signal aftersaid length register has been decremented to a first predeterminedvalue; means responsive to said first signal to cause said lengthregister to again store said indication of the length of said sequence;and repeat means responsive to said first signal for causingretransmission of said sequence from said storage means to said usingdevice.
 3. The data expansion apparatus of claim 2, wherein said controlmeans further comprises:error detecting means connected to said firstregister means for generating an error signal in response topredetermined data configurations occurring in said first registermeans.
 4. The data expansion apparatus of claim 2 wherein said controlmeans further includes error detecting means comprising:means fordetecting a predetermined value occurring in one, but not both, of saidlength and number of repetition indications stored in said firstregister means.
 5. The data expansion apparatus of claim 2 wherein saidcontrol means further includes:a count register; means connecting saidfirst register means to said count register to cause said count registerto store said indication of the number of repetitions of said sequence;second decrementing means responsive to said first detecting means tocause decrementation of said count register each time said sequence istransmitted from said storage means to said using device; seconddetecting means connected to said count register for generating a secondsignal after said count register has been decremented to a secondpredetermined value; and means connecting said second detecting means tosaid repeat means and to said second decrementing means in such mannerthat said second signal, when it occurs, will inhibit the operation ofsaid repeat means and of said second decrementing means.